The n-XYTER ASIC was developed in context of the EU-FP6 Integrated Infrastructure Initiative NMI3 in the Joint Research Activity DETNI as the common read-out solution for three different, solid converter based neutron counting area detectors. Because of the the statistical, non-triggerable nature of neutron data to be processed, the internal architecture of the chip is self triggered and data driven. It integrates 128 channels with low noise preamplifiers and shapers. Each channel has two different shapers with distinct time constants, one optimized for timing resolution, the other one optimized for energy (pulse height) resolution. A peak detector connected to the slower shaper allows for the application of a spectroscopic amplitude measurement. An internal time stamp generator provides the temporal reference that may be employed to identify time coincidences of signals on different detector channels and thus correlate their spatial point of origin. For testability and calibration purposes, a charge injector with adjustable pulse height was implemented. The bias settings and various other parameters can be controlled via a standard I2C-interface.
-- WalterFJMueller - 30 Apr 2008
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![]() | nXYTER.pdf | manage | 2926.4 K | 15 Dec 2009 - 16:06 | MarcusHoehl | nXYTER Reference Manual V1.5, 15.12.2009 |